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CY25702
Programmable High-Frequency Crystal Oscillator (XO)
Features
* Programmable High-frequency Crystal Oscillator (XO) * Wide output (CLK) range from: -- 1.0 to 125 MHz (VDD = 5.0V) -- 1.0 to 90 MHz (VDD = 3.3V) * Integrated phase-locked loop (PLL) * Low cycle-to-cycle Jitter * 3.3/5.0V operation * Output Enable function * Power-down function * Refer to CY25701 for SSCG function * Lead-free package
Benefits
* Eliminates the need for external crystal oscillator. * Internal PLL to generate up to 125-MHz output. * Suitable for most PC, consumer and networking applications. * Application compatibility in standard and low-power systems. * CY25701 can be used as a direct replacement in 3.3V applications if Spread Spectrum Clock (SSC) is required for EMI reduction without any PCB modification. * In-house programming of samples and prototype quantities is available using the CY3672 programming kit and CY36xx socket adapter. Sample and production quantities are available through Cypress's value-added distribution partners.
Logic Block Diagram
Pin Configuration
CY25702 4-pin Plastic SMD
RFB
PLL
1
CXIN PROGRAMMABLE CONFIGURATION CXOUT OUTPUT DIVIDERS and MUX
OE/PD# VSS
VDD 4 CLK 3
3 CLK
2
1 OE/PD#
4 VDD
2 VSS
Cypress Semiconductor Corporation Document #: 38-07721 Rev. **
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised December 09, 2004
CY25702
Pin Definition
Pin 1 2 3 4 OE/PD# VSS CLK VDD Name Description Output Enable pin: Active HIGH. If OE = 1, CLK is enabled. Power Down pin: Active LOW. If PD# = 0, Power Down is enabled. Power supply ground. Clock output. 3.3V or 5.0V power supply. The CY25702 uses a programmable configuration memory array to synthesize output frequency. The frequency CLK output can be programmed from 10-125 MHz. The CY25702 is available in a 4-pin plastic SMD packages with operating temperature range of -20 to 70C. Output Enable/Power Down OE/PD# 1 N/A ENTER DATA Power Supply VDD 4 V ENTER DATA
Functional Description
The CY25702 is a Crystal Oscillator (XO). The device uses a Cypress proprietary PLL to synthesize the frequency of the embedded input crystal. Table 1. Programming Data Requirement Pin Function Pin Name Pin# Units Program Value Output Frequency CLK 3 MHz ENTER DATA
Programming Description
Field/Factory-Programmable CY25702 Field/Factory programming is available for samples and manufacturing by Cypress and its distributors. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. Once the request has been processed, you will receive a new part number, samples, and data sheet with the programmed values. This part number will be used for additional sample requests and production orders. Additional information on the CY25702 can be obtained from the Cypress web site at www.cypress.com. Output Frequency, CLK Output (CLK, pin 3) The frequency at the CLK output is produced by synthesizing the embedded crystal oscillator frequency input. The range of
synthesized clock is from 1-125MHz when VDD= 5V and 1-90MHz when VDD = 3.3V. Output Enable or Power Down (OE/PD#, pin 1) Pin 1 can be programmed as either output enable (OE) or Power Down (PD#).
Absolute Maximum Rating
Supply Voltage (VDD).....................................-0.5V to +7.0V DC Input Voltage ................................... -0.5V to VDD + 0.5V Storage Temperature (Non-condensing) .... -55C to +100C Junction Temperature ................................ -40C to +125C Data Retention @ Tj = 125C................................> 10 years Package Power Dissipation...................................... 350 mW
Operating Conditions
Parameter VDD1 VDD2 TA CLOAD FCLK1 FCLK2 TPU Description Supply Voltage Range Supply Voltage Range Ambient Temperature Max. Load Capacitance @ pin 3 CLK output frequency, CLOAD = 15 pF, VDD = 5.0V CLK output frequency, CLOAD = 15 pF, , VDD = 3.3V Power-up time for VDD to reach minimum specified voltage (power ramp must be monotonic) Min. 3.00 4.50 -20 - 1.0 1.0 0.05 Typ. 3.30 5.00 - - - - - Max. 3.60 5.50 70 15 125 90 500 Unit V V C pF MHz MHz ms
DC Electrical Characteristics
Parameter VOH1 VOL1 Description High Output Voltage Low Output Voltage Condition VDD = 5.0V, IOH = -16mA VDD= 5.0V , IOL= 16mA Min. VDD-0.4 - Typ. - - Max. - 0.4 Unit V V
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CY25702
DC Electrical Characteristics
Parameter VOH2 VOL2 VIH1 VIL1 VIH2 VIL2 IIH IIL IOZ CIN IVDD1 IVDD2 IVDD3 IVDD4 IPD# FS AG SR Description High Output Voltage Low Output Voltage Input High Voltage (pin 1) Input Low Voltage (pin 1) Input High Voltage (pin 1) Input Low Voltage (pin 1) Input High Current (pin 1) Input Low Current (pin 1) Input Capacitance (pin 1) Supply Current Supply Current Supply Current Supply Current Power Down Current Frequency Stability Aging Shock Resistance Condition VDD = 3.3V , IOH = -8mA VDD= 3.3V , IOL = 8mA VDD = 5.0V VDD = 5.0V VDD = 3.3V VDD = 3.3V Vin = VDD Vin = VSS Pin 1, OE or PD# VDD = 3.3V, CLK = 1 to 90 MHz, CLOAD = 0, OE = VDD VDD = 3.3V, CLK = 1 to 90 MHz, CLOAD = 0, OE = GND VDD = 5.0V, CLK = 1 to 125 MHz, CLOAD = 0, OE = VDD VDD = 5.0V, CLK = 1 to 125 MHz, CLOAD = 0, OE = GND PD# = GND -20 to +70C Ta = 25C, First Year Three drops on a hard board from 750 mm or excitation test with 29.400m/s2 x 0.3ms x 1/2 sinewave in three directions Min. VDD-0.4 - 2.0 - 0.7VDD - - - -10 - - - - - - -50 -5 -20 Typ. - - - - - - - - - 5 - - - - - - - - Max. - 0.4 - 0.8 - 0.2VDD 10 10 10 7 28 16 45 30 50 50 5 20 Unit V V V V V V A A A pF mA mA mA mA A ppm ppm ppm
Output Leakage Current (pin 3) Three-state output, OE = 0
AC Electrical Characteristics
Parameter DC tR tF TOE1 TOE2 TLOCK TSU TPDD Description Output Duty Cycle Output Rise Time Output Fall Time Condition CLK, Measured at VDD/2 20%-80% of VDD, CL = 15 pF 20%-80% of VDD, CL = 15 pF Min. 40 - - - - - - - Typ. 50 - - 150 150 - - - Max. 60 4.0 4.0 350 350 10 5 25 Unit % ns ns ns ns ms ms ns
Output Disable Time (pin1 = OE) Time from falling edge on OE to stopped outputs (Asynchronous) Output Enable Time (pin1 = OE) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) PLL Lock Time Power Down Delay Time Time for CLK to reach valid frequency PD# pin Low to CLK Low (Asynchronous) Start-up time out of Power Down PD# pin Low to High
Application Circuit
Power
VDD 1 OE/PD# VDD 4 0.1uF CLK 3
(GND if PD#)
CY25702
2 VSS
Document #: 38-07721 Rev. **
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CY25702
Switching Waveforms
Duty Cycle Timing (DC = t1A/t1B)
CLK t1A t1B
Output Rise/Fall Time
CLK
Tr Tf Output Rise time (Tr) = 20 to 80% of VDD Output Fall time (Tf) = 80 to 20% of VDD
VDD 0V
Output Enable/Disable Timing
OUTPUT ENABLE VDD 0V VIL VIH TOE2
CLK TOE1
High Impedance
Document #: 38-07721 Rev. **
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CY25702
Ordering Information
Part Number[1,2] CY25702JXCZZZZ CY25702JXCZZZZT CY25702FJXC CY25702FJXCT CY25702XZZZ CY25702XZZZT CY25702FX CY25702FXT Package description 4-Lead Plastic JE04A SMD - Lead-free 4-Lead Plastic JE04A SMD, Tape and Reel - Lead-free 4-Lead Plastic JE04A SMD - Lead-free 4-Lead Plastic JE04A SMD, Tape and Reel - Lead-free 4-Lead Plastic JE04B SMD - Lead-free 4-Lead Plastic JE04B SMD, Tape and Reel - Lead-free 4-Lead Plastic JE04B SMD - Lead-free 4-Lead Plastic JE04B SMD, Tape and Reel - Lead-free Product Flow Commercial, -20 to 70C Commercial, -20 to 70C Commercial, -20 to 70C Commercial, -20 to 70C Commercial, -20 to 70C Commercial, -20 to 70C Commercial, -20 to 70C Commercial, -20 to 70C
Package Drawings and Dimensions
4-Lead JEC JE04A
10.20.3 (10.5 MAX) 4 1.00.2 (1.0)
5.0 5.60.2 (5.8 MAX)
3.6
1.00.2 (1.0) 1 1.3
2.1 2.4 2.5 (2.7 MAX)
+0.2 -0.1
4.6 0.1 0.51 0.150.1 (0.05 MIN) 5.080.1
DIMENSIONS IN MILLIMETERS REFERENCE JEDEC: N/A PKG. WEIGHT: 0.24 gms
5.08 RECOMMENDED SOLDERING PATTERN
51-85204-*A
Notes: 1. "ZZZZ" or "ZZZ" denotes the assigned product dash number. This number will be assigned by factory after the output frequency and spread percent programming data is received from the customer. 2. "FJXC" or "FX" suffix is used for products programmed in field by Cypress distributors.
Document #: 38-07721 Rev. **
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CY25702
Package Drawings and Dimensions (continued)
4-Lead JE (5.0 x 2.8 MM) JE04B
5.00.2
4 0.35 MIN.
2.8
3.20.2
2.50.2
0.35 MIN. 1
0.5 1.0 1.6
1.10.1
1.2 MAX. 0.1 2.540.1 0.050.05 (0 MIN.) 2.2
1.5
DIMENSIONS IN MILLIMETERS REFERENCE JEDEC: N/A PKG. WEIGHT: 0.034 gms
2.54 RECOMMENDED SOLDERING PATTERN
51-85212-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07721 Rev. **
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY25702
Document History Page
Document Title: CY25702 Programmable High-Frequency Crystal Oscillator (XO) Document Number: 38-07721 REV. ** ECN NO. 296081 Issue Date See ECN Orig. of Change RGL New data sheet Description of Change
Document #: 38-07721 Rev. **
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